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contents in this document are subject to change without notice. no part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of lcd driver ic team. precautions for light light has characteristics to move electrons in t he integrated circuitry of semiconductors, therefore may change the characteristics of semiconductor devices when irradiated with light. consequently, the users of the packages which may expose chips to external light such as cob, cog, tcp and cof must con sider effective methods to block out light from reaching the ic on all parts of the surface area, the top, bottom and the sides of the chip. follow the precautions below when using the products. 1. consider and verify the protection of penetrating light to t he ic at substrate ( board or glass) or product design stage. 2. always test and inspect products under the environment with no penetration of light. s 6b 07 29 102 seg / 8 1 com driver & controller for 4 gray scale stn lcd jun.19 . 2001 . ver. 0 . 1
102 seg / 81 com driver & controller for stn lcd s6b 0729 x 2 s6b0729 specification revision history version content date 0 .0 preliminary specification (short form) june 8, 2001 0 . 1 prel iminary specification (full set) june 19, 2001
s6b 0729x 102 seg / 81 com driver & controller for stn lcd 3 co ntents introduction ................................ ................................ ................................ ................................ ............ 1 features ................................ ................................ ................................ ................................ .................... 1 block diagram ................................ ................................ ................................ ................................ ......... 3 pad configuration ................................ ................................ ......... ? ! ????? F???? ?? ???? . pad center coordinates ................................ ................................ ................................ ............................... 6 pin description ................................ ................................ ................................ ................................ ........ 6 power supply ................................ ................................ ................................ ................................ .... 9 lcd driver supply ................................ ................................ ................................ ............................ 9 system control ................................ ................................ ................................ ............................... 10 microprocessor inter face ................................ ................................ ................................ ......... 11 lcd driver outputs ................................ ................................ ................................ ......................... 13 functional description ................................ ................................ ................................ ...................... 14 microprocessor inter face ................................ ................................ ................................ ......... 14 display data ram (dd ram ) ................................ ................................ ................................ .............. 18 lcd display circuits ................................ ................................ ................................ ....................... 21 lcd driver circuit ................................ ................................ ................................ ........................... 26 power supply circuit s ................................ ................................ ................................ .................. 29 referece circuit exa mples ................................ ................................ ................................ .......... 34 reset circuit ................................ ................................ ................................ ................................ .... 36 instruction description ................................ ................................ ................................ ..................... 37 specifications ................................ ................................ ................................ ................................ ........ 60 absolute maximum rat ings ................................ ................................ ................................ ........... 60 dc characteristics ................................ ................................ ................................ ........................ 61 ac characteristics ................................ ................................ ................................ ......................... 64 reference applica tions ................................ ................................ ................................ ..................... 68 microprocessor inter face ................................ ................................ ................................ ......... 68 connections between s6b0729 and lcd pane l ................................ ................................ ......... 70

s6b 0729x 102 seg / 81 com driver & controller for stn lcd 1 introduction the s6b0729 is a driver & controller lsi for 4 - level gray scale graphic dot - matrix liquid crystal display systems. it contains 1 0 2 segment and 8 1 common driver circuits. this chip is connected directly to a microprocessor, accepts serial peripheral interface (spi) or 8 - bit parallel display data and stores in an on - chip display data ram of 1 0 2 x 8 1 x 2 bits . it performs display data ram read/write operation with no external operating clock to minimize power consumption. in addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components. features 4 - level ( w hite, l ight g ray, d a rk g ray, b lack) g ray s cale d isplay with pwm and frc m ethod s ddram data [2n: 2n+1] 00 01 10 11 gray scale white light gray dark gray dark (accessible c olumn a ddress, n = 0, 1, 2, ?? , 99, 100, 101) driver output circuits - 1 02 segment outputs / 8 1 common outputs applicable duty ratios d uty ratio applicable lcd bias maximum display area 1/16 ~ 1/ 80 (icon disabled) 1/17 ~ 1/ 8 1 (icon enabled) 1/4 to 1/1 0 8 1 1 0 2 - various partial display - partial window moving & data scrolling on - chip display data ram - capa city: 8 1 1 0 2 2 = 16,524 bits microprocessor interface - 8 - bit parallel bi - directional interface with 6800 - series or 8080 - series - spi ( serial p eripheral interface ) available (only write operation) on - chip l ow p ower analog circuit - on - chip oscillator circui t - voltage converter ( x3, x4, 5 ) - voltage regulator ( t emperature coefficient : - 0.125%/ c, or external input ) - on - chip e lectronic contrast control function (64 steps) - voltage follower (lcd bias : 1/4 to 1/10 ) operating voltage range - supply voltage (v dd ): 1.8 to 3.3 v - converter input voltage(vci): 2.4 to 3.3 v - lcd driving voltage (v lcd = v0 - v ss ): 4.0 to 1 1 .0 v
102 seg / 81 com driver & controller for stn lcd s6b 0729 x 2 low power consumption - 60 m a typ. (o peration ) : vdd=vci=2.5v, vlcd=9.004v, x5 boosting, no load - 2 m a m ax. ( sleep mo de) package type - gold bumped c hip or tcp
s6b 0729x 102 seg / 81 com driver & controller for stn lcd 3 block diagram vdd v0 v1 v2 v3 v4 vss vr intrs ref vext vci c1- c1+ c2- c2+ c3+ c4+ vout v / c circuit v / r circuit v / f circuit 41 common driver circuits mpu interface (parallel & serial ) instruction decoder bus holder column address circuit line address circuit page address circuit display data ram 81 x1 02 x 2 = 16 , 524 bits display data control circuit display timing generator circuit common output controller circuit db0 db1 db2 db3 db4 db5 db6( sclk ) db7 (sid) rw_wr e_rd rs cs1b p s 0 ps1 resetb coms1 com79 : com40 seg101 seg100 seg99 : : seg2 seg1 seg0 com39 : com0 coms0 oscillator 1 02 segment driver circuits 41 common driver circuits i/o buffer status register instruction register test s osc1 figure 1 . block diagram
102 seg / 81 com driver & controller for stn lcd s6b 0729 x 4 pin description power supply table 3. power supply pin description name i/o description vdd supply power supply v ss supply ground lcd driver supply voltages the voltage determined by lcd pixel is impedance - converted by an operational amplifier for application. voltages should have the following relationship; v0 3 v1 3 v2 3 v3 3 v4 3 v ss when the internal power circuit i s active, these voltages are generated as following table according to the state of lcd bias. lcd bias v1 v2 v3 v4 1/n bias (n - 1) / n x v0 (n - 2) / n x v0 (2/n) x v0 ( 1/ n) x v0 v0 v1 v2 v3 v4 i/o note: n = 4,5,9,10 lcd driver supply table 4. lcd driver supply pin de scription name i/o description c1 - o capacitor 1 negative connection pin for voltage converter c1+ o capacitor 1 positive connection pin for voltage converter c2 - o capacitor 2 negative connection pin for voltage converter c2+ o capacitor 2 positive co nnection pin for voltage converter c 3 + o capacitor 3 positive connection pin for voltage converter c 4 + o capacitor 4 positive connection pin for voltage converter v0 i/o lcd power supply input / output pin connect this pin to vss through capacitor vout i/o voltage converter input / output pin connect this pin to vss through capacitor vcl i voltage converter input voltage pin vr i v0 voltage adjustment pin it is valid only when on - chip resistors are not used (intrs = "l") when using internal resistors (intrs = " h ") , open this pin ref i selects the external vref voltage via the vext pin - ref = ? h ? : u sing the internal vref - ref = ? l ? : u sing the external vref v ext i externally input reference voltage (vref) for the internal voltage regulator it is vali d only when ref is "l" when using internal voltage regulator, connect to vdd, vss or open this pin
s6b 0729x 102 seg / 81 com driver & controller for stn lcd 5 osc1 i when using internal clock oscillator, connect a resistor between osc1 and vdd.
102 seg / 81 com driver & controller for stn lcd s6b 0729 x 6 system control table 5. system c ontrol pin description name i/o desc ription intrs i internal resistor select pin this pin selects the resistors for adjusting v0 voltage level - intrs = "h": use the internal resistors. - intrs = "l": use the external resistors vr pin and external resistive divider control v0 voltage tests o test pins don?t use th is pin. - tests: open this pin.
s6b 0729x 102 seg / 81 com driver & controller for stn lcd 7 microprocessor inter face table 6. microprocessor i nterface pin description name i/o description reset b i reset input pin when reset b is ?l?, initialization is executed. paral lel / serial data input select input ps 0 interface mode data / instruction data read / write serial clock h parallel rs db0 to db7 e_rd rw_wr - l serial rs or none sid (db7) write only sclk (db6) ps 0 i *note: in serial mode , it is impossible to read data from the on - chip ram. and db0 to db5 are high impedance and e_rd and rw_wr must be fixed to either ?h? or ?l?. ps1 i microprocessor interface select input pin - ps0 = ? h ? , ps1 = "h": 6800 - series parallel mpu interface - ps0 = ? h ? , ps1 = "l": 8080 - s eries parallel mpu interface - ps0 = ? l ? , ps1 = "h": 4 p in - spi mpu interface - ps0 = ? l ? , ps1 = "l": 3 p in - spi mpu interface csb i chip select input pins data/instruction i/o is enabled only when csb is "l". when chip select is non - active, db0 to db7 ma y be high impedance. rs i register select input pin - rs = "h": db0 to db7 are display dat a - rs = "l": db0 to db7 are control data read / write execution control pin c68 mpu type rw_wr description h 6800 - series rw read / write control inpu t pin - rw = ?h? : r ead - rw = ?l? : w rite l 8080 - series /wr write enable clock input pin the data on db0 to db7 are latched at the rising edge of the /wr signal. rw _wr i
102 seg / 81 com driver & controller for stn lcd s6b 0729 x 8 table 7. microprocessor i nterface pin description (continued) name i/o description read / write execution control pin ps1 mpu type e_rd description h 6800 - series e read / write control input pin - rw = ?h?: when e is ?h?, db0 to db7 are in an output status. - rw = ?l?: the data on db0 to db7 are latched at the falling edge of the e signal. l 8080 - series /rd read enable clock input pin when /rd is ?l?, db0 to db7 are in an output status. e_rd i db0 to db7 i/o 8 - bit bi - directional data bus that is connected to the standard 8 - bit microp rocessor data bus. when the serial interface selected (ps 0 = "l"); - db0 to db5: high impedance - db6: serial input clock (sclk) - db7: serial input data (sid) when chip select is not active, db0 to db7 may be high impedance.
s6b 0729x 102 seg / 81 com driver & controller for stn lcd 9 lcd driver outputs table 8. lcd d river o utput pin description name i/o description lcd segment driver outputs the display data and the m signal control the output voltage of segment driver. segment driver output voltage display data m (internal) normal disp lay reverse display h h v0 v2 h l v ss v3 l h v2 v0 l l v3 v ss power save mode v ss v ss seg 0 to seg 101 o lcd common driver outputs the internal scanning data and m signal control the output voltage of common driver. scan data m (intern al) common driver output voltage h h v ss h l v0 l h v1 l l v4 power save mode v ss com 0 t o com 79 o coms (coms1) o common output for the icons the output signals of two pins are same. when not used, these pins should be left open. note: dummy ? these p ins should be opened (floated).
102 seg / 81 com driver & controller for stn lcd s6b 0729 x 10 functional description microprocessor interface chip select input there is csb pin for chip selection. the s6b0729 can interface with an mpu when csb is "l". when these pins are set to any other combination, rs, e_rd, and r w_wr inputs are disabled and db0 to db7 are to be high impedance. and, in case of serial interface, the internal shift register and the counter are reset. parallel / serial interface s6b0729 has four types of interface with an mpu, which are two serial and two parallel interface s . this parallel or serial interface is determined by ps pin as shown in table 9 . table 9 . parallel / serial interface mode type ps1 csb ps 0 interface mode h 6800 - series mpu mode parallel l csb h 8080 - series mpu mode h 4 - p in spi mode serial l c sb l 3 - p in spi mode parallel interface (ps 0 = "h") the 8 - bit bi - directional data bus is used in parallel interface and the type of mpu is selected by ps1 as shown in table 10 . the type of data transfer is determined by signals at rs, e_rd and rw_wr as shown in table 11 . table 10 . microprocessor selection for parallel interface ps1 csb rs e_rd rw_wr db0 to db7 mpu bus h csb rs e rw db0 to db7 6800 - series l csb rs /rd /wr db0 to db7 8080 - series table 11 . parallel data transfer commo n 6800 - series 8080 - series rs e_rd (e) rw_wr (rw) e_rd (/rd) rw_wr (/wr) description h h h l h display data read out h h l h l display data write l h h l h register status read l h l h l writes to internal register (i ns truction) note: when e_rd pin is always pulled high for 6800 - series interface, it can be used csb for enable signal. in this case, interface data is latched at the rising edge of csb and t he type of data transfer is determined by signals at rs, rw_wr as in case of 6800 - series mode .
s6b 0729x 102 seg / 81 com driver & controller for stn lcd 11 cs1b rs rw e db command write data w rite status read data read figure 5. 6800 - series mpu interface protocol (ps= ? h ? , mi= ? h ? ) cs1b rs /wr /rd db command write data w rite status read data read figure 6. 8080 - series mpu interface protocol (ps= ? h ? , mi= ? l ? ) serial interface (ps 0 = "l") when the s6b0729 is active (csb= ? l ? ) , seria l data (db7) and serial clock (db6) inputs are enabled. and not active, the internal 8 - bit shift register and the 3 - bit counter are reset. the display data/command indication may be controlled either via software or the register select(rs) pin, based on th e setting of ps1. when the rs pin is used (ps1 = ? h ? ), data is display data when rs is high, and command data when rs is low. when rs is not used (ps1 = ? l ? ), the lcd driver will receive command from mcu by default. if messages on the data pin are data rat her than command, mcu should send data direction command(11101000) to control the data direction and then one more command to define the number of data bytes will be write. after these two continuous commands are send, the following messages will be data r ather than command. serial data can be read on the rising edge of serial clock going into db6 and processed as 8 - bit parallel data on the eighth serial clock. and the ddram column address pointer will be increased by one automatically. the next bytes after the display data string is handled as command data.
102 seg / 81 com driver & controller for stn lcd s6b 0729 x 12 serial mode ps0 ps1 csb rs 4 - pin spi mode l h csb used 3 - pin spi mode l l csb not used 4 - p in spi mode (ps 0 = "l" , ps1 = " h ") cs b sid sclk rs db6 db7 db0 db1 db2 db3 db4 db5 db6 db7 figure 2 . 4 - p in spi timing (rs is used)
s6b 0729x 102 seg / 81 com driver & controller for stn lcd 13 3 - p in spi mode (ps 0 = "l" , ps1 = " l ") to write data to the ddram, send data direction command in 3 - p in spi mode. data is latched at the rising edge of s clk. and the ddram column address pointer will be increased by one automatically . (1) set page and column address. set page address : 1 0 1 1 p3 p2 p1 p0 set column address msb : 0 0 0 1 0 y6 y5 y4 set column address lsb : 0 0 0 0 y3 y2 y1 y0 (2) set ddc(data direction command) and no. of data bytes. set data direction command ( for spi mode only): 1 1 1 0 1 0 0 0 set no. of data bytes : d7 d6 d5 d4 d3 d2 d1 d0 (3) this figure is example for 104 data bytes to be transfered . (1) ( s clk csb 829 830 831 0 0 1 7 8 15 23 sid msb data in page lsb ddc no. of data 3 byte (1) 2 byte (2) 104 byte 0 figure 3 . 3 - p in spi timing (rs is not used) this command is used in 3 - p in spi mode only. it will be two continuous commands, the first byte control s the data direction and inform s the lcd driver the s econd byte will be number of data bytes will be write. after these two commands sending out, the following messages will be data. if data is stopped in transmitting, i t i s not valid data. new d ata will be transferred serially with most significant bit firs t. note: in spite of transmission of d ata, if csb will be disable, state terminates abnormally. next state is initialized. busy flag the b usy f lag indicates whether the s6b0729 is operating or not. when db7 is "h" in read status operation, this device is in busy status and will accept only read status instruction. if the cycle time is correct, the microprocessor needs not to check this flag before each instruction, which improves the mpu performance.
102 seg / 81 com driver & controller for stn lcd s6b 0729 x 14 data transfer the s6b0729 uses bus holder and internal data bus for data transfer with the mpu. when writing data from the mpu to on - chip ram, data is automatically transferred from the bus holder to the ram as shown in figure 5 . and when reading data from on - chip ram to the mpu, the data for the initial read cycle is stored in the bus holder (dummy read) and the mpu reads this stored data from bus holder for the next data read cycle as shown in figure 6 . this means that a dummy read cycle must be inserted between each pair of address sets when a sequence of ad dress sets is executed. t herefore, the data of the specified address cannot be output with the r ead d isplay d ata instruction right after the address sets, but can be output at the second read of data. rs /wr db0 to db7 n d(n) d(n+1) d(n+2) d(n+3) internal signals mpu signals /wr bus holder column address n n+1 n+2 n+3 n d(n) d(n+1) d(n+2) d(n+3) figure 4 . write timing
s6b 0729x 102 seg / 81 com driver & controller for stn lcd 15 rs /wr /rd db0 to db7 n mpu signals dummy d(n) d(n+1) internal signals /wr /rd bus holder column address n d(n) d(n+1) d(n+2) n n+1 n+2 n+3 d(n+2) figure 5 . read timing
102 seg / 81 com driver & controller for stn lcd s6b 0729 x 16 display data ram (dd ram) the display data ram stores pixel data for the lcd. it is 81 - row (10 page by 8 bits & icon page by 1 bit) by 102 - column addressable array. each pixel can be selected when the page and column addresses are specified. data is read from or written to the 8 lines of each page directly through db0 to db7. the display data of db0 to db7 from the microprocessor correspond to the lcd common li nes . t he microprocessor can read from and write to ram through the i/o buffer. since the lcd controller operates independently, data can be written into ram at the same time as data is being displayed without causing the lcd flicker. page address circuit t his circuit is for providing a page address to d isplay d ata ram shown in figure 8 . it incorporates 4 - bit page address register changed by only the ?set page? instruction. page address 11 is a special ram area for the icons and display data db0 is only vali d. line address circuit this circuit assigns ddram a line address corresponding to the first line (com 0 ) of the display. therefore, by setting line address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of on - chip ram as shown in figure 8 . it incorporates 7 - bit line address register changed by only the initial display line instruction and 7 - bit counter circuit. at the beginning of each lcd frame, the contents of register are copied to the line co unter which is increased by cl signal and generates the line address for transferring the 102 - bit ram data to the display data latch circuit .
s6b 0729x 102 seg / 81 com driver & controller for stn lcd 17 column address circuit column address circuit has a n 8 - bit preset counter that provides column address to the d is play d ata ram as shown in figure 8 . when set column address msb / lsb instruction is issued, 7 - bit [y 7 :y 1 ] are set and lowest bit, y0 is set to ? 0 ? . s ince this address is increased by 1 each a r ead or w rite d ata instruction, microprocessor can access the d isplay data continuously. however, the counter is not increased and locked if a non - existing address above 65h. it is unlocked if a column address is set again by set column address msb / lsb instruction. and the column address counter is independent of pa ge address counter. adc s elect instruction makes it possible to invert the relationship between the column address and the segment outputs. it is necessary to rewrite the display data on built - in ram after issuing adc s elect instruction. refer to the foll owing figure 7 . seg output seg 0 seg 1 seg 2 seg 3 ... ... seg 98 seg 99 seg 100 seg 101 column address [y 7 :y 1 ] 00h 01h 02h 03h ... ... 62 h 63 h 64 h 65 h internal c olumn address [y7:y0] 00 hex 01 hex 02 hex 03 hex 04 hex 05 hex 06 hex 07 hex ... ... c4 he x c5 hex c6 hex c7 hex c8 hex c9 hex ca hex cb hex display data (adc = 0) 1 1 1 0 0 0 0 1 ... ... 1 0 1 1 0 0 0 1 lcd panel display ... ... display data (adc = 1 ) 0 1 0 0 1 1 1 0 ... ... 0 1 0 0 1 0 1 1 lcd panel display ... ... fig ure 7 . the relationship b etween t he column address a nd the segment outputs segment control circuit this circuit controls the display data by the d isplay on / off, r everse d isplay on / off and e ntire d isplay on / off instructions without changing the data in the display data ram.
102 seg / 81 com driver & controller for stn lcd s6b 0729 x 18 seg101 seg100 seg1 seg0 seg99 seg98 seg97 seg96 seg2 seg3 seg4 seg5 - - - - - adc=1 adc=0 column address lcd output initial start line address = 08h 00 - - - - - 01 02 03 04 05 60 61 62 63 64 65 00 - - - - - 01 02 03 04 05 60 61 62 63 64 65 page 0 page 2 page 1 page 3 page9 page 10 line address page address db3 db0 db1 db2 data db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 00h 08h 07h 06h 05h 04h 03h 02h 01h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 18h 17h 16h 15h 14h 13h 12h 11h 19h 1ah 1bh 1ch 1dh 1eh 1fh page 8 page 7 page 9 40h 41h 42h 43h 44h 4ch 4bh 4ah 49h 48h 47h 46h 45h 4dh 4eh 4fh 38h 39h 3ah 3bh 3ch 3fh 3eh 3dh 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 com output com72 com1 com0 com79 com78 com77 com75 com76 com74 com73 com2 com11 com10 com9 com8 com7 com5 com6 com4 com3 com12 com21 com20 com19 com18 com17 com15 com16 com14 com13 com22 com59 com58 com57 com56 com55 com53 com54 com52 com23 com60 com69 com68 com67 com66 com65 com63 com64 com62 com61 com70 com71 coms com51 com49 com50 com48 1/73duty start = 08h end = 07h 1/81duty initial line register = 08h figure 8 . display data ram map
s6b 0729x 102 seg / 81 com driver & controller for stn lcd 19 lcd display circuits frc (frame rate control) and pwm (pulse width modulation) function circuit the s6b0729 incorporates an frc function and a pwm function circuit to displ ay a 4 - level gray scale. the frc function and pwm utilize liquid crystal characteristics whose transmittance is changed by an effective value of applied voltage. the s6b0729 provides four 4 - bit palette - registers to assign the desired gray level. th e se regi ster s are set by the instructions and the resetb. - gray s cale t able of 4 frc (frame rate control) gray s cale l evel msb (db7 to db4) lsb (db3 to db0) 2nd fr (fr2) 1st fr (fr1) white 4th fr (fr4) 3rd fr (fr3) 2nd fr (fr2) 1st fr (fr1) light g ray 4th fr (fr4) 3rd fr (fr3) 2nd fr (fr2) 1st fr (fr1) dark g ray 4th fr (fr4) 3rd fr (fr3) 2nd fr (fr2) 1st fr (fr1) black 4th fr (fr4) 3rd fr (fr3) - gray s cale t able of 3 frc (frame rate control) gray s cale l evel msb (db7 to db4) lsb (db3 to db0) 2nd f r (fr2) 1st fr (fr1) white 3rd fr (fr3) 2nd fr (fr2) 1st fr (fr1) light g ray 3rd fr (fr3) 2nd fr (fr2) 1st fr (fr1) dark g ray 3rd fr (fr3) 2nd fr (fr2) 1st fr (fr1) black 3rd fr (fr3)
102 seg / 81 com driver & controller for stn lcd s6b 0729 x 20 - gray s cale t able of 15 pwm (puls e width modulation) dec hex 4 - b its pwm (on width) note 0 00 0000 0 (0/15) brighter 1 01 0001 1/15 2 02 0010 2/15 3 03 0011 3/15 4 04 0100 4/15 5 05 0101 5/15 6 06 0110 6/15 7 07 0111 7/15 8 08 1000 8/15 9 09 1001 9/15 10 0a 1010 10/15 11 0b 1011 11/15 12 0c 1100 12/ 1 5 13 0d 1101 13/15 14 0e 1110 14/15 15 0f 1111 1 (15/15) darker - gray s cale t able of 12 pwm (pulse width modulation) dec hex 4 - b its pwm (on width) note 0 00 0000 0 (0/12) brighter 1 01 0001 1/12 2 02 0010 2/12 3 03 0011 3/12 4 04 0100 4/12 5 05 0101 5/12 6 06 0110 6/12 7 07 0111 7/12 8 08 1000 8/12 9 09 1001 9/12 10 0a 1010 10/12 11 0b 1011 11/12 12 0c 1100 1 (12/12) darker 13 0d 1101 0/12 14 0e 1110 0/12 15 0f 1111 0/12 this area is selected to off level (0/12 level)
s6b 0729x 102 seg / 81 com driver & controller for stn lcd 21 - gray s cale t able of 9 pwm (pulse width modulation) dec hex 4 - b its pwm (on width) note 0 00 0000 0 (0/9) brighter 1 01 0001 1/9 2 02 0010 2/9 3 03 0011 3/9 4 04 0100 4/9 5 05 0101 5/9 6 06 0110 6/9 7 07 011 1 7/9 8 08 1000 8/9 9 09 1001 1 (9/9) darker 10 0a 1010 0/9 11 0b 1011 0/9 12 0c 1100 0/9 13 0d 1101 0/9 14 0e 1110 0/9 15 0f 1111 0/9 this area is selected to off level (0/9 level)
102 seg / 81 com driver & controller for stn lcd s6b 0729 x 22 oscillator this is on - chip o scillator with external resi stor. i ts frequency is controlled by external re s istor between osc1 and vdd. this o scillator signal is used in the voltage converter and display timing generation circuit. display timing generator circuit this circuit generates some signals to be used for displaying lcd. the display clock, cl (internal) , generated by oscillation clock, generates the clock for the line counter and the signal for the display data latch. the line address of on - chip ram is generated in synchronization with the display clock and the display data latch circuit latches the 102 - bit display data in synchronization with the display clock. the display data, which is read to the lcd driver, is completely independent of the access to the display data ram from the microprocessor. the displ ay clock generates an lcd ac signal (m) which enables the lcd driver to make a ac drive waveform, and also generates an internal common timing signal and start signal to the common driver. the frame signal or the line signal changes the m by setting intern al instruction. driving waveform and internal timing signal are shown in figure 9. fr(internal) m(internal) 12 7 12 8 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 cl(internal) com0 v0 v1 v2 v3 v4 vss com1 v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss segn 95 96 97 98 99 100 101 102 figure 9 . 2 - frame ac driving waveform (duty ratio = 1/ 102 )
s6b 0729x 102 seg / 81 com driver & controller for stn lcd 23 fr(internal) m(internal) 12 7 12 8 1 2 3 4 5 6 7 8 9 10 11 12 93 94 95 96 97 98 99 100 101 102 1 2 3 4 cl(internal) com0 v0 v1 v2 v3 v4 vss com1 v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss segn figure 10 . n - line inversion driving waveform (n = 5, dut y ratio = 1/ 102 )
102 seg / 81 com driver & controller for stn lcd s6b 0729 x 24 lcd driver circuit this driver circuit is configured by 81 - c hannel common drivers and 1 02 - channel segment drivers. this lcd panel driver voltage depends on the combination of display data and m signal. com 0 com 1 com 2 com 3 com 4 com 5 com 6 com 7 com 8 com 9 com1 0 com1 1 com1 2 com1 3 com1 4 com 15 s e g 4 s e g 3 s e g 2 s e g 1 s e g 0 seg 2 seg 1 seg 0 com 2 com 0 com 1 m v0 v1 v2 v3 v4 v ss v0 v1 v2 v3 v4 v ss v0 v1 v2 v3 v4 v ss v0 v1 v2 v3 v4 v ss v0 v1 v2 v3 v4 v ss v0 v1 v2 v3 v4 v ss v dd v ss figure 11 . segment and common timing
s6b 0729x 102 seg / 81 com driver & controller for stn lcd 25 partial display on lcd the s6b0729 realizes the partial display function on lcd with low - duty driving for saving power consumption and showing the various display duty. to show the various display duty on lcd, lcd driving dut y and bias are programmable via the instruction. and, built - in power supply circuits are controlled by the instruction for adjusting the lcd driving voltages -- com0 -- com1 -- com2 -- com3 -- com4 -- com5 -- com6 -- com7 -- com8 -- com9 -- com10 -- com11 -- com12 -- com13 -- com14 -- com15 -- com16 -- com17 -- com18 -- com19 -- com20 -- com21 -- com22 -- com23 figure 12 . reference example for partial display -- com0 -- com1 -- com2 -- com3 -- com4 -- com5 -- com6 -- com7 -- com8 -- com9 -- com10 -- com11 -- com12 -- com13 -- com14 -- com15 -- com16 -- com17 -- com18 -- com19 -- com20 -- com21 -- com22 -- com23 figure 13 . partial display (partial display duty = 16 , initial com0 = 0)
102 seg / 81 com driver & controller for stn lcd s6b 0729 x 26 -- com0 -- com1 -- com2 -- com3 -- com4 -- com5 -- com6 -- com7 -- com8 -- com9 -- com10 -- com11 -- com12 -- com13 -- com14 -- com15 -- com16 -- com17 -- com18 -- com19 -- com20 -- com21 -- com22 -- com23 figure 14 . moving display (partial display duty = 16 , initial com0 = 8)
s6b 0729x 102 seg / 81 com driver & controller for stn lcd 27 power supply circuit s the p ower s upply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power consumption and the fewest components. there are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. they are controlled by p ower c ontrol instructio n. for details, refers to "instruction description". table 12 shows the referenced combinations in using p ower s upply circuits. table 12 . recommended power supply combinations user setup power control (vc vr vf) v/c circuits v/r circuits v/f circuits vout v0 v1 to v4 only the internal power supply circuits are used 1 1 1 o n o n o n open open open only the voltage regulator circuits and voltage follower circuits are used 0 1 1 o ff o n on external input open open only the voltage follower circuits are used 0 0 1 o ff o ff o n open external input open only the external power supply circuits are used 0 0 0 o ff o ff o ff open external input external input
102 seg / 81 com driver & controller for stn lcd s6b 0729 x 28 voltage converter circuits these circuits boost up the electric potential between vci and vss to 3, 4, 5 time s toward positive side and boosted voltage is outputted from vout pin. it is possible to select the lower boosting level in any boosting circuit by ?set dc - dc step - up? instruction. when the higher level is selected by instruction, vout voltage is not valid . [c1 = 1.0 to 4.7 m f] vss vout c3+ c1- c1+ c2+ c2 - c4+ vss vci c1 - + vout = 3 x vci c1 - + c1 - + - vss vout c3+ c1- c1+ c2+ c2 - c4+ vss vci c1 - + c1 - + c1 - + - c1 - + - vout = 4 x vci figure 15 . three times boosting circuit figure 16 . four times boosting circuit vss vout c3+ c1- c1+ c2+ c2 - c4+ vss vci c1 - + c1 - + c1 - + - c1 - + - c1 - + vout = 5 x vci figure 17 . five times boosting circuit
s6b 0729x 102 seg / 81 com driver & controller for stn lcd 29 voltage regulator circuits the function of the in ternal v oltage r egulator circuits is to determine liquid crystal operating voltage, v0, by adjusting resistors, ra and rb, within the range of |v0| < |vout|. because vout is the operating voltage of operational - amplifier circuits shown in figure18 , it is n ecessary to be applied internally or externally. for the eq. 1, we determine v0 by ra, rb and v ev . the ra and rb are connected internally or externally by intrs pin. and v ev called the voltage of electronic volume is determined by eq. 2, where the paramet er a is the value selected by instruction, "set reference voltage register", within the range 0 to 63. v ref voltage at ta= 25 c is shown in table 13 . rb v0 = (1 + ? ? ? ? ) x v ev [v] ------ (eq. 1) ra (63 - a ) v ev = (1 - ? ? ? ? ? ? ) x v ref [v] ------ (eq. 2) 2 1 0 table 13 . v ref voltage at ta = 25 c ref temp. coefficient v ref [ v ] 1 - 0.125 % / c 2. 1 0 external input vext v ev gnd ra rb vss vr v0 vout + - figure 18 . internal voltage regulator circuit
102 seg / 81 com driver & controller for stn lcd s6b 0729 x 30 in case of using internal resistors, ra and rb (intrs = "h?) when intrs pin is " h " , resistor ra is connected internally between vr pin and v ss , and rb is connected between v0 and vr. we determine v0 by two instructions, "regulator resistor select" and "set reference voltage". table 14 . internal rb / ra ratio depending on 3 - bit data (r2 r1 r0) 3 - bit data settings (r2 r1 r0) 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 + (rb / r a) 2. 3 3. 0 3 . 7 4 . 4 5 . 1 5 . 8 6 . 5 7 . 2 figure 19 shows v0 voltage measured by adjusting internal regulator register ratio (rb / ra) and 6 - bit electronic volume registers for each temperature coefficient at ta = 25 c. 0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 16.00 0 8 16 24 32 40 48 56 electronic volume register (0 to 63) (1, 1, 1) 63 (1, 1, 0) (1, 0, 1) (1, 0 ,0) (0, 1, 1) (0, 1, 0) (0, 0, 1) (0, 0, 0) v0 voltage [v] figure 19 . electronic volume level (temp. coefficient = - 0.125 % / c)
s6b 0729x 102 seg / 81 com driver & controller for stn lcd 31 in case of using external resistors, ra and rb (intrs = "l") when intrs pin is " l " , it is necessary to connect external regulator resistor ra between vr and vss, and rb between v0 and vr. example: for the following requirements 1. lcd driver voltage, v0 = 10v 2. 6 - bit reference voltage register = (1, 0, 0, 0, 0, 0) 3. maximum current flowing ra, rb = 1 ua from eq. 1 rb 10 = (1 + ? ? ? ) x v ev [v] -- ---- (eq. 3) ra from eq. 1 (63 - 32) v ev = (1 - ? ? ? ? ? ? ) x 2. 1 = 1. 7 9 [v] ------ (eq. 4) 2 1 0 from requirement 3. 10 ? ? ? ? ? = 1 [ua] ------ (eq. 5) ra + rb from equations eq . 3, 4 and 5 ra = 1. 7 9 [m w ] rb = 8. 2 1 [m w ] table 15 shows the range of v0 depending on the above requirements. table 15. the r ange of v0 electronic volume level 0 ....... 32 ....... 63 v0 8.21 . ...... 10.00 ....... 11.73 voltage follower circuits vlcd voltage (v0) is resistively divided into four voltage levels (v1, v2, v3 and v4), and those output impedance are converted by the v oltage f ollower for increasing drive capability. table 16 shows the relationship between v1 to v4 level and each duty ratio. table 16. the relationship between v1 to v4 level and each duty ratio lcd bias v1 v2 v3 v4 remarks 1/ n ( n - 1)/ n x v0 ( n - 2 )/ n x v0 2/ n x v0 1/ n x v0 n = 4,5 ,9,10
102 seg / 81 com driver & controller for stn lcd s6b 0729 x 32 discharge circuit when power save mode instruction is executed or the power supply switched off, the vlcd voltages(v0,v1,v2,v3,v4) are discharged forcibly by this circuit.
s6b 0729x 102 seg / 81 com driver & controller for stn lcd 33 reference circuit ex amples [c1 = 1.0 to 4.7 [ m f], c2 = 0.47 to 2.0 [ m f]] when using internal regulator resistors when not using internal regulator resistors v ss c1 c1 c1 c1 c1 + + + + + v dd intrs vout vr v4 v3 v2 v1 v0 c4+ c2 - c2+ c1+ c1 - c3+ v ss c1 c1 c1 c1 c1 + + + + + vout vr v4 v3 v2 v1 v0 c4+ c2 - c2+ c1+ c1 - c3+ v ss rb ra c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 intrs figure 20. when using a ll lcd power circuits (5 - time v/c: o n , v/r: o n , v/f: o n ) [c2 = 0.47 to 2.0 [ m f]] when using internal regulator resistors when not using internal regulator resistors intrs v ss ra rb v ss v dd intrs v ss external power supply external power supply c2 - + c2 - + c2 - + c2 - + c2 - + vout c3+ c1- c1+ c2+ c2- c4+ vr v0 v1 v2 v3 v4 c2 - + c2 - + c2 - + c2 - + c2 - + vout c3+ c1- c1+ c2+ c2- c4+ vr v0 v1 v2 v3 v4 figure 21. when using s ome lcd power circuits (v/c: o ff , v/r: o n , v/f: o n )
102 seg / 81 com driver & controller for stn lcd s6b 0729 x 34 [c2 = 0.47 to 2.0 [ m f]] v dd intrs v ss external power supply c2 - + c2 - + c2 - + c2 - + c2 - + vout c3+ c1- c1+ c2+ c2- c4+ vr v0 v1 v2 v3 v4 figure 22. when using s ome lcd power circuits (v/c: o ff , v/r: o ff , v/f: o n ) [c2 = 0.47 to 2.0 [ m f]] v dd intrs v ss external power supply vout c3+ c1- c1+ c2+ c2- c4+ vr v0 v1 v2 v3 v4 figure 23. when not using a ny internal lcd power supply circuits (v/c: o ff , v/r: o ff , v/f: o ff )
s6b 0729x 102 seg / 81 com driver & controller for stn lcd 35 reset circuit setting resetb to ?l? or reset instruction can initialize internal function. when resetb becomes ?l?, following procedure is occurred. page address: 0 column address: 0 r ead - m odify - write : off display on / off: off initial display line: 0 (firs t) initial com0 register: 0 (com0) partial display duty ratio: 1/ 80 reverse display on / off: off (normal) n - line inversion register: 0 (disable) entire display on/off: off icon control register on/off: off (icon disable) power control register (vc, vr , vf) = ( 0 , 0, 0) dc - dc converter circuit = (0, 0) regulator resistor select register: (r2, r1, r0) = (0, 0, 0) contrast level: 32 lcd bias ratio: 1/ 9 com scan direction: 0 adc select: 0 oscillator: off power save mode: release display data length regist er: 0 (for spi mode) white mode set: off white palette register (wg3, wg2, wg1, wg0) = (0, 0, 0, 0) light gray mode set: off light gray palette register (lg3, lg2, lg1, lg0) = (0, 0, 0, 0) dark gray mode set: off dark gray palette register (dg3, dg2, dg1, dg0) = (1, 1, 1, 1) black mode set: off black palette register (bg3, bg2, bg1, bg0) = (1, 1, 1, 1) frc, pwm mode: 4frc, 9pwm when reset instruction is issued, following procedure is occurred. page address: 0 column address: 0 r ead - m odify - write : off init ial display line: 0 (first) regulator resistor select register: (r2, r1, r0) = ( 0, 0 , 0) contrast level: 32 display data length register: 0 (for spi mode) white mode set: off white palette register (wg3, wg2, wg1, wg0) = (0, 0, 0, 0) light gray mode set: off light gray palette register (lg3, lg2, lg1, lg0) = (0, 0, 0, 0) dark gray mode set: off dark gray palette register (dg3, dg2, dg1, dg0) = (1, 1, 1, 1) black mode set: off black palette register (bg3, bg2, bg1, bg0) = (1, 1, 1, 1) frc, pwm mode: 4frc, 9 pwm while resetb is ?l? or r eset instruction is executed, no instruction except read status can be accepted. reset status appears at db4. after db4 becomes ?l?, any instruction can be accepted. resetb must be connected to the reset pin of the mpu, and init ialize the mpu and this lsi at the same time. the initialization by resetb is essential before used.
102 seg / 81 com driver & controller for stn lcd s6b 0729 x 36 instruction description table 17 . instruction table : don?t care instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 description read d isplay d ata 1 1 r ead data read data from ddram write d isplay d ata 1 0 write data write data into ddram read s tatus 0 1 busy on res mf2 mf1 mf0 ds1 ds0 read the internal status icon control register on/off 0 0 1 0 1 0 0 0 1 icon icon = 0 : icon disable (default) icon = 1 : ico n enable & set the page address to 16 set p age a ddress 0 0 1 0 1 1 p3 p2 p1 p0 set page address set c olumn a ddress msb 0 0 0 0 0 1 0 y 7 y 6 y 5 set column address msb set c olumn a ddress lsb 0 0 0 0 0 0 y 4 y 3 y 2 y 1 set column address lsb s et m odify - read 0 0 1 1 1 0 0 0 0 0 set modify - read mode reset m odify - read 0 0 1 1 1 0 1 1 1 0 release modify - read mode display o n /o ff 0 0 1 0 1 0 1 1 1 d d=0: display off d=1: display on 0 0 0 1 0 0 0 0 set i nitial d isplay l ine r egister 0 0 s6 s5 s4 s3 s2 s1 s0 2 - byte i n struction to specify the initial display line to realize vertical scrolling 0 0 0 1 0 0 0 1 set i nitial com0 r egister 0 0 c6 c5 c4 c3 c2 c 1 c0 2 - byte i nstruction to specify the initial com0 to realize window scrolling 0 0 0 1 0 0 1 0 set p artial di splay d uty r atio 0 0 d6 d5 d4 d3 d2 d1 d0 2 - byte i nstruction to set partial display duty ratio 0 0 0 1 0 0 1 1 set n - line i nversion 0 0 n 4 n3 n2 n 1 n0 2 - byte i nstruction to set n - line inversion register release n - line i nversion 0 0 1 1 1 0 0 1 0 0 release n - line inversion mode reverse d isplay on/off 0 0 1 0 1 0 0 1 1 rev rev=0: normal display, rev=1: reverse display entire d isplay on/off 0 0 1 0 1 0 0 1 0 eon eon=0: normal display. eon= 1: entire display on
s6b 0729x 102 seg / 81 com driver & controller for stn lcd 37 table 1 7 . instruction table (continued) : don?t care instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 description power c ontrol 0 0 0 0 1 0 1 vc vr vf control power circuit operation select dc - dc s tep - up 0 0 0 1 1 0 0 1 dc1 d c0 select the step - up of the internal voltage converter select r egulator r esistor 0 0 0 0 1 0 0 r2 r1 r0 select internal resistance ratio of the regulator resistor 0 0 1 0 0 0 0 0 0 1 set electronic volume register 0 0 e v5 e v4 e v3 e v2 e v1 e v0 2 - byte i nstruction to specify the refer ence voltage select lcd b ias 0 0 0 1 0 1 0 b2 b1 b0 select lcd bias shl s elect 0 0 1 1 0 0 shl com bi - directional selection shl=0: normal direction shl=1: reverse direction adc s elect 0 0 1 0 1 0 0 0 0 adc s eg bi - directional selection adc=0: normal direction adc=1: reverse direction oscillator o n start 0 0 1 0 1 0 1 0 1 1 start the built - in oscillator set p ower s ave m ode 0 0 1 0 1 0 1 0 0 p p=0: normal mode p=1: sleep mode release p ower s ave m ode 0 0 1 1 1 0 0 0 0 1 release power save mode reset 0 0 1 1 1 0 0 0 1 0 initialize the internal functions 1 1 1 0 1 0 0 0 set d ata d irection & display data length(ddl) d7 d6 d5 d4 d 3 d2 d1 d0 2 - byte i nstruction to specify the number of data bytes. ( spi mode ) nop 0 0 1 1 1 0 0 0 1 1 no operation test instruction 0 0 1 1 1 1 don't use this instruction.
102 seg / 81 com driver & controller for stn lcd s6b 0729 x 38 table 1 7 . instruction table (continued) instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 description set frc and pwm mode 0 0 1 0 0 1 0 frc pwm1 pwm0 frc(1:3frc, 0:4frc) pwm1 pwm0 0 0 9pwm 0 1 9pwm 1 0 12pwm 1 1 15pwm 0 0 1 0 0 0 1 0 0 0 set white mode and 1 st /2 nd frame, set pulse width 0 0 wb3 wb2 wb1 wb0 wa3 wa2 wa1 wa 0 set white mode and 1 st /2 nd frame 0 0 1 0 0 0 1 0 0 1 set white mode and 3 rd /4 th frame, set pulse width 0 0 wd3 wd2 wd1 wd0 wc3 wc2 wc1 wc0 set white mode and 3 rd /4 th frame 0 0 1 0 0 0 1 0 1 0 set light gray mode and 1 st /2 nd frame, set pulse width 0 0 lb3 lb2 lb1 lb0 la3 la2 la1 la0 set light gray mode and 1 st /2 nd fr ame 0 0 1 0 0 0 1 0 1 1 set light gray mode and 3 rd /4 th frame, set pulse width 0 0 ld3 ld2 ld1 ld0 lc3 lc2 lc1 lc0 set light gray mode and 3 rd /4 th frame 0 0 1 0 0 0 1 1 0 0 set dark gray mode and 1 st /2 nd frame, set pulse width 0 0 db3 db2 d b 1 db0 da3 da2 da1 da0 set dark gray mode and 1 st /2 nd frame 0 0 1 0 0 0 1 1 0 1 set dark gray mode and 3 rd /4 th frame, set pulse width 0 0 dd3 dd2 dd1 dd0 dc3 dc2 dc1 dc0 set dark gray mode and 3 rd /4 th frame 0 0 1 0 0 0 1 1 1 0 set bl a ck mod e and 1 st /2 nd frame, set pulse width 0 0 bb3 bb2 bb1 bb0 ba3 ba2 ba1 ba0 set bl a ck mode and 1 st /2 nd frame 0 0 1 0 0 0 1 1 1 1 set bl a ck mode and 3 rd /4 th frame, set pulse width 0 0 bd3 bd2 bd1 bd0 b c3 bc2 bc1 bc0 set bl a ck mode and 3 rd /4 th frame
s6b 0729x 102 seg / 81 com driver & controller for stn lcd 39 read display data 8 - bit data from d isplay d ata ram specified by the column address and page address can be read by this instruction. as the column address is incre as ed by 1 automatically after each this instruction, the microprocessor ca n continuously read data from the addressed page. a dummy read is required after loading an address into the column address register. display d ata cannot be read through the serial interface. rs rw db7 db6 db5 db4 db3 db2 db1 db0 1 1 read data write disp lay data 8 - bit data of d isplay d ata from the microprocessor can be written to the ram location specified by the column address and page address. the column address is incre as ed by 1 automatically so that the microprocessor can continuously write data to th e addressed page. during auto - increment, the column address wraps to 0 after the last column is written rs rw db7 db6 db5 db4 db3 db2 db1 db0 1 0 write data data write set column address set page address optional status column = column + 1 no yes data write continue ? dummy data read set column address set page address optional status column = column + 1 no yes data read continue ? data read column = column + 1 figure 24 . sequence for writing display data figure 25 . sequence for reading display data
102 seg / 81 com driver & controller for stn lcd s6b 0729 x 40 read status indicates the internal status of the s6b0729 rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 1 busy on / off res mf2 mf1 mf0 ds1 ds0 flag description busy the device is busy when internal operation or reset. any instruction is rejected until busy goes low. 0: chip is active, 1: chip is being busy on / off indicates display on / off status 0: display o ff , 1: display o n res et indicates the initialization is in progress by reset signal. 0: chip is act ive, 1: chip is being reset mf manufacturer id, mf2 mf1 mf0 = [0 0 0] ds display size id, ds1 ds0 = [1 0] icon control register on/off this instruction makes icon enable or disable. by default, icon display is disabled (icon= 0). when icon control regis ter is set to ? 1 ? , icon display is enabled and page address is set to ? 16 ? . then user can write data for icons. it is impossible to set the page address to ? 16 ? by set page address instruction. therefore, when writing data for icons, icon control register on instruction would be used to set the page address to ? 16 ? . when icon control register is set to ? 0 ? , icon display is disabled. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 0 1 icon icon = 0 : icon disable (default) icon = 1 : icon enable & set the page address to 16
s6b 0729x 102 seg / 81 com driver & controller for stn lcd 41 set page address sets the p age a ddress of display data ram from the microprocessor into the page address register. any ram data bit can be accessed when its page address and column address are specified. along with the column address, the p age a ddress defines the address of the display ram to write or read display data. changing the p age a ddress doesn't effect to the display status. set page address instruction can not be used to set the page address to ? 10 ? . use icon control register o n/off instruction to set the page address to ? 10 ? . rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 1 p3 p2 p1 p0 p3 p2 p1 p0 p age 0 0 0 0 0 0 0 0 1 1 : : : : : 1 0 0 1 9 1 0 1 0 10 set column address sets the c olumn a ddress of display ram from th e microprocessor into the column address register. along with the c olumn a ddress, the c olumn a ddress defines the address of the display ram to write or read display data. when the microprocessor reads or writes display data to or from display ram, co lumn a ddresses are automatically incre as ed. set column address msb rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 1 0 y 7 y 6 y 5 set column address lsb rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 y 4 y 3 y 2 y 1 y 7 y 6 y 5 y 4 y 3 y 2 y 1 c olumn address [y7:y1] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : 1 1 0 0 1 0 0 100 1 1 0 0 1 0 1 101
102 seg / 81 com driver & controller for stn lcd s6b 0729 x 42 set modify - r ead this instruction stops the automatic increment of the column address by the r ead d isplay d ata instruction, but the column address is still increase d by the w rite d isplay d ata instruction. and it reduces the load of microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others. this mode is canceled by the r eset modify - r ead instruction. rs rw db7 db6 db5 db4 db 3 db2 db1 db0 0 0 1 1 1 0 0 0 0 0 reset modify - read this instruction cancels the modify - r ead mode, and makes the column address return to its initial value just before the s et modify - read instruction is started. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 1 1 1 0 set modify-read reset modify-read set page address data process no yes change completed? set column address (n) dummy read data read data write return column address (n) figure 26 . sequence for cursor display
s6b 0729x 102 seg / 81 com driver & controller for stn lcd 43 display on / off turns the display on or off . this command has priority over entire display on/off and reverse display on/off. commands are accepted while the display is off, but the visual state of the display does not change. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 1 1 d on d on = 1: display on d on = 0: display off set initial display line register sets the line address of display ram to determine the ini tial display line using 2 - byte instruction. the ram display data is displayed at the top of row(com0) of lcd panel. the 1 st instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 0 0 0 the 2 nd instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 s 6 s 5 s 4 s 3 s 2 s 1 s 0 s 6 s 5 s 4 s 3 s 2 s 1 s 0 line address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 2 : : : : : : : : 1 0 0 1 1 1 0 78 1 0 0 1 1 1 1 79 1 0 1 0 0 0 0 : : : : : : : 1 1 1 1 1 1 1 2 nd i nstruction (2- b yte i nstruction for r egister s etting) setting i initial d isplay l ine e nd 1 st i nstruction (2- b yte i nstruction for m ode s etting) setting i nitial d isplay l ine s tart figure 27 . the sequence for setting the initial display line
102 seg / 81 com driver & controller for stn lcd s6b 0729 x 44 set initial com0 register sets the initial row (com) of the lcd panel using the 2 - byte instruction. by using this instruction, it is possible to realize the window moving without the change of display data. the 1 st instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 0 0 1 the 2 nd instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 c6 c5 c4 c3 c2 c1 c0 c6 c5 c4 c3 c2 c1 c0 initial com0 0 0 0 0 0 0 0 com0 0 0 0 0 0 0 1 com1 0 0 0 0 0 1 0 com2 0 0 0 0 0 1 1 com3 : : : : : : : : 1 0 0 1 1 0 0 com 76 1 0 0 1 1 0 1 com 77 1 0 0 1 1 1 0 com 78 1 0 0 1 1 1 1 com 79 2 nd i nstruction ( i nitial com0 s etting) setting i nitial com0 e nd 1 st i nstruction ( m ode s etting) setting i nitial com0 s tart figure 28 . sequence for setting the initial com0
s6b 0729x 102 seg / 81 com driver & controller for stn lcd 45 set partial display duty ratio se ts the duty ratio within range of 16 to 80 (icon disabled) or 17 to 81 (icon enabled) to realize partial display by using the 2 - byte instruction. the 1 st instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 0 1 0 the 2 nd instruction rs rw db 7 db6 db5 db4 db3 db2 db1 db0 0 0 x d6 d5 d4 d3 d2 d1 d0 d6 d5 d4 d3 d2 d1 d0 selected partial duty ratio (icon disabled) selected partial duty ratio (icon enabled) 0 0 0 0 0 0 0 : : : : : : : 0 0 0 1 1 1 1 no operation no operation 0 0 1 0 0 0 0 1/ 16 1/ 17 0 0 1 0 0 0 1 1/1 7 1/1 8 : : : : : : : : : 1 0 0 1 1 1 1 1/ 79 1/ 80 1 0 1 0 0 0 0 1/ 80 1/ 81 1 0 1 0 0 0 1 : : : : : : : 1 1 1 1 1 1 1 no operation no operation 2 nd i nstruction ( p artial d isplay d uty s etting) setting p artial d isplay e nd 1 st i nstruction ( m ode s etting) setting p artial d isplay s tart figure 29 . sequence for setting partial displa y
102 seg / 81 com driver & controller for stn lcd s6b 0729 x 46 set n - line inversion register sets the inverted line number within range of 3 to 3 3 to improve the display quality by controlling the phase of the internal lcd ac signal (m) by using the 2 - byte instruction. the dc - bias problem could be occurred if k is even number. so, we recommend customers to set k to be odd number. k : d/n d : the number of display duty ratio (d is selectable by customers) n : n for n - line inversion (n is selectable by customers). the 1 st instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 0 1 1 the 2 nd instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 n4 n3 n2 n1 n0 n4 n3 n2 n1 n0 selected n - line inversion 0 0 0 0 0 0 - line inversion (frame inversion) 0 0 0 0 1 3 - line inversion 0 0 0 1 0 4 - line inversion 0 0 0 1 1 5 - line inversion : : : : : : 1 1 1 0 1 3 1 - line inversion 1 1 1 1 0 3 2 - line inversion 1 1 1 1 1 3 3 - line inversion 2 nd i nstruction ( n - l ine i nversion s etting) setting n - l ine i nversion e nd 1 st i nstruction ( m ode s etting) setting n - l ine i nversion s tart figure 30 . sequence for n - line inversion release n - line inversion returns to the frame inversion condition from the n - line inversion condition. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 1 0 0
s6b 0729x 102 seg / 81 com driver & controller for stn lcd 47 reverse display on / off reverses the display status on lcd panel without rewriting the cont ents of the display data ram. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 1 1 rev rev ddram data = ? 00 ? ? white ddram data = ? 0 1? ? light gray ddram data = ?1 0 ? ? dark gray ddram data = ? 11 ? ? dark 0 (normal) white ( ? 00 ? ) light gray ( ? 01 ? ) dar k gray ( ? 10 ? ) dark ( ? 11 ? ) 1 (reverse) dark ( ? 11 ? ) dark gray ( ? 10 ? ) light gray ( ? 01 ? ) white ( ? 00 ? ) entire display on / off forces the whole lcd points to be turned on regardless of the contents of the display data ram. at this time, the contents of the display data ram are held. this instruction has priority over the r everse display o n / o ff instruction. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 1 0 eon e on ddram data = ? 00 ? ? white ddram data = ? 0 1? ? light gray ddram data = ?1 0 ? ? dark gr ay ddram data = ? 11 ? ? dark 0 (normal) white ( ? 00 ? ) light gray ( ? 01 ? ) dark gray ( ? 10 ? ) dark ( ? 11 ? ) 1 ( entire ) dark ( ? 11 ? ) dark ( ? 11 ? ) dark ( ? 11 ? ) dark ( ? 11 ? ) power control selects one of eight power circuit functions by using 3 - bit register. an externa l power supply and part of internal power supply functions can be used simultaneously. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 0 1 vc vr vf vc vr vf status of internal power supply circuits 0 1 internal voltage converter circuit is off intern al voltage converter circuit is on 0 1 internal voltage regulator circuit is off internal voltage regulator circuit is on 0 1 internal voltage follower circuit is off internal voltage follower circuit is on
102 seg / 81 com driver & controller for stn lcd s6b 0729 x 48 select dc - dc step - up selects one of 3 dc - dc step - up to reduce the power consumption by this instruction. it is very useful to realize the partial display function. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 1 0 0 1 dc1 dc0 dc1 dc0 selected dc - dc converter circuit 0 0 3 times boosting cir cuit 0 1 4 times boosting circuit 1 0 5 times boosting circuit select regulator resistor selects resistance ratio of the internal resistor used in the internal voltage regulator. see voltage regulator section in power supply circuit. refer to the t abl e 1 4 . rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 0 0 r2 r1 r0 r2 r1 r0 1+ ( rb / ra ) 0 0 0 2.3 0 0 1 3.0 0 1 0 3.7 0 1 1 4.4 1 0 0 5.1 1 0 1 5.8 1 1 0 6.5 1 1 1 7.2
s6b 0729x 102 seg / 81 com driver & controller for stn lcd 49 set electronic volume register consist of 2 - byte instruction s the 1 st ins truction set reference voltage mode , the 2 nd one updates the contents of reference vol tage register. after second instruction, reference voltage m ode is released. the 1 st instruction : set reference voltage select m ode rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 0 0 0 0 0 1 the 2 nd instruction : set reference voltage r egister rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 e v5 e v4 e v3 e v2 e v1 e v0 e v5 e v4 e v3 e v2 e v1 e v0 reference voltage p arameter ( a ) 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63 2 nd instruction for register setting setting r eference v oltage end 1 st instruction for mode setting setting r eference v oltage start figure 31 . sequence for setting the electronic volume
102 seg / 81 com driver & controller for stn lcd s6b 0729 x 50 select lcd bias selects lcd bias ratio of the voltage required for driving the lcd. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 1 0 b2 b1 b0 b2 b1 b0 lcd bias 0 0 0 1/ 4 0 0 1 1/ 5 0 1 0 1/6 - 0 1 1 1/7 1 0 0 1/8 1 0 1 1/ 9 1 1 0 1/ 10 1 1 1 1/10 shl select com output scanning direction is selected by this instruction which determines the lcd driver output status. rs rw d b7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 0 0 shl : don ? t care shl = 0: normal direction (com 0 ? com 79 ) shl = 1: reverse direction (com 79 ? com 0 ) adc select changes the relationship between ram column address and segment driver. the direction of segment driver output pins c ould be reversed by software. this makes ic layout flexible in lcd module asse mbly. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 0 0 adc adc = 0: normal direction (seg 0 ? seg 101 ) adc = 1: reverse direction (seg 101 ? seg 0 )
s6b 0729x 102 seg / 81 com driver & controller for stn lcd 51 oscillator on start this instruction enables the built - in oscillator circuit. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 0 1 1 power save the s6b0729 enters the power save status to reduce the power consumption to the static power consumption value and returns to the normal operation status by the following instructions. set power save mode rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 0 0 p p = 0: normal mode p = 1: sleep mode release power save mode rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 0 1 sleep mode oscillator circuits: off lcd power supply circuits: off all com / seg output level: vss consumption current < 2 ua set power save mode (sleep mode) release power save mode (sleep mode) figure 32 . power save routine
102 seg / 81 com driver & controller for stn lcd s6b 0729 x 52 reset this inst ruction r esets initial display line, column address, page address, and common output status select to their initial status, but dose not affect the contents of display data ram. this instruction cannot initialize the lcd power supply , which is initialized by the resetb pin. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 1 0 set data direction & display data length (3 - pin spi mode) consists of 2 bytes instruction. this command is used in 3 - pin spi mode only (ps0 = ? l ? and ps1 = ? l ? ) . it will be two continuous commands, the first byte control the data direction (write mode only) and inform the lcd driver the second byte will be number of data bytes will be write. when rs is not used, the display data length instruction is used to indicate that a spe cified number of display data bytes are to be transmitted. the next byte after the display data string is handled as command data. the 1 st instruction: set data direction (only write mode) rs rw db7 db6 db5 db4 db3 db2 db1 db0 x x 1 1 1 0 1 0 0 0 the 2 nd instruction: set display data length (ddl) register rs rw db7 db6 db5 db4 db3 db2 db1 db0 x x d7 d6 d5 d4 d3 d2 d1 d 0 d7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 display data length 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 2 0 0 0 0 0 0 1 0 3 : : : : : : : : : 1 1 1 1 1 1 0 1 254 1 1 1 1 1 1 1 0 255 1 1 1 1 1 1 1 1 256 nop no operation rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 1 1
s6b 0729x 102 seg / 81 com driver & controller for stn lcd 53 test instruction this instruction is for testing ic. please do not use it. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 1 s et pwm & frc mode selects 3/4 frc and 9 / 12 / 15 pwm rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 0 1 0 frc pwm1 pwm0 frc pwm1 pwm0 status of pwm & frc 0 1 4frc 3frc 0 0 1 1 0 1 0 1 9pwm 9pwm 12pwm 15pwm
102 seg / 81 com driver & controller for stn lcd s6b 0729 x 54 set gray scale mode & register consists of 2 bytes instruction. the first byte sets grayscale mode and the second byte updates the contents of gray scale register without issuing any other instruction. - set gray scale mode rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 0 0 1 gm2 gm1 gm0 gm2 gm1 gm0 description 0 0 0 in case of setting white mode and 1 st / 2 nd frame 0 0 1 in case of setting white mode and 3 rd / 4 th frame 0 1 0 in case of setting light gray mode and 1 st / 2 nd frame 0 1 1 in case of setting light gray mode and 3 rd / 4 th frame 1 0 0 in case of setting dark gray mode and 1 st / 2 nd frame 1 0 1 in case of setting dark gray mode and 3 rd / 4 th frame 1 1 0 in case of setting black mode and 1 st / 2 nd frame 1 1 1 in case of setting black mode and 3 rd / 4 th frame - set gray scale register rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 gb3 gb2 gb1 gb0 ga3 ga2 ga1 ga0 0 0 gd3 gd2 gd1 gd0 gc3 gc2 gc1 gc0 ga3, gb3, gc3, gd3 ga2, gb2, gc2, gd2 ga1, gb1, gc1, gd1 ga0, gb0, gc0, gd0 pulse w idth (9pwm) pulse w idth (12pwm) p ulse w idth (15pwm) 0 0 0 0 0/9 0/12 0/15 0 0 0 1 1/9 1/12 1/15 : : : : : : : 1 0 0 1 9/9 9/12 9/15 1 0 1 0 0/9 10/12 10/15 1 0 1 1 0/9 11/12 11/15 1 1 0 0 0/9 12/12 12/15 1 1 0 1 0/9 0/12 13/15 1 1 1 0 0/9 0/12 14/15 1 1 1 1 0/9 0/12 15/15 * ga3=wa3,la3,da3,ba3 ga2=wa2,la2,da2,ba2 ga1=wa1,la1,da1,ba1 ga0=wa0,la0,da0,ba0 gb3=wb3,lb3,db3,bb3 ga2=wb2,lb2,db2,bb2 ga1=wb1,lb1,db1,bb1 ga0=wb0,lb0,db0,bb0 gc3=wc3,lc3,dc3,bc3 ga2=wc2,lc2,dc2,bc2 ga1=wc1,lc1,dc1,bc1 ga0=wc0,lc0,dc0,bc0 gd3=wd3,ld3,dd3,bd3 ga2=wd2,ld2,dd2,bd2 ga1=wd1,ld1,dd1,bd1 ga0=wd0,ld0,dd0,bd0
s6b 0729x 102 seg / 81 com driver & controller for stn lcd 55 referential instruction set - up flow: initializing with the built - in power supply circuits user system setup by external pins start of initialization power on (vdd-vss) keeping the resetb pin = "l" waiting for stabilizing the power resetb pin = "h" user application setup by internal instructions [display duty select] [adc select] [shl select] [com0 register select] user lcd power setup by internal instructions [oscillator on] [dc-dc step-up register select] [regulator resistor select] [electronic volume register select] [lcd bias register select] waiting for stabilizing the lcd power levels end of initialization [ gray-scale select] user lcd p ower setup by internal instructions [voltage converter on] user lcd p ower setup by internal instructions [voltage regulator on] user lcd p ower setup by internal instructions [voltage follower on] waiting for 50% rising of vout waiting for 3 1ms figure 33 . initializing with the b uilt - in p ower s u pply c ircuits
102 seg / 81 com driver & controller for stn lcd s6b 0729 x 56 referential instruction set - up flow: initializing with out the built - in power supply circuits user system setup by external pins start of initialization power on (vdd-vss) keeping the resetb pin = "l" waiting for stabilizing the power set power save user application setup by internal instructions [display duty select] [adc select] [shl select] [com0 register select] user lcd power setup by internal instructions [oscillator on] regulator or follower register select [power control] waiting for stabilizing the lcd power levels end of initialization resetb pin = "h" release power save [gray-scale select] figure 34 . initializing without the b uilt - in p ower s upply c ircuits
s6b 0729x 102 seg / 81 com driver & controller for stn lcd 57 referential instruction set - up flow: data display ing end of initialization write display data by instruction [display data write] turn display on / off instruction [display on / off] end of data display display data ram addressing by instruction [initial display line] [set page address] [set column address] figure 35 . data d isplaying r eferential instruction set - up flow: power off optional status power off (vdd-vss) end of power off set power save by instruction figure 36. power o ff
102 seg / 81 com driver & controller for stn lcd s6b 0729 x 58 referential instruction set - up flow: partial duty changing start of partial changing set display off by internal [display on / off] set partial duty by internal instructions [partial display duty ratio select] [initial display line register] [com0 register select] user lcd power setup by internal instructions [dc-dc step-up register select] [regulator resistor select] [electronic volume register select] [lcd bias register select] [power control] waiting for stabilizing the lcd power levels end of partial changing release power save set s leep mode by internal instruction [power save mode] write display data & display on by internal instruction [display data write] [display on / off] waiting for discharging the lcd power levels [gray-scale select] figure 37 . partial duty changing
s6b 0729x 102 seg / 81 com driver & controller for stn lcd 59 specifications absolute maximum rat ings table 18 . absolute maximum ratings (v ss = 0v) parameter symbol rating unit v dd - 0.3 ~ + 7.0 v v0, vout - 0.3 ~ + 17 .0 v supply voltage range v1, v2, v3, v4 - 0.3 ~ v0 + 0.3 v external re ference voltage vext +0.3 ~ v dd input voltage range v in - 0.3 ~ v dd + 0.3 v operating temperature range t opr - 40 ~ + 85 c storage temperature range t str - 55 ~ + 125 c notes: 1. v dd, v0, vout, v1 to v4 and vext are based on v ss = 0v. 2. voltages v0 3 v1 3 v2 3 v3 3 v4 3 vss must always be satisfied. (vlcd = v0 ? vss) 3. if supply voltage exceeds its absolute maximum range, this lsi may be damaged permanently. it is desirable to use this lsi under electrical characteristic conditions during gene ral operation. otherwise, this lsi may malfunction or reduced lsi reliability may result.
102 seg / 81 com driver & controller for stn lcd s6b 0729 x 60 dc characteristics table 19. dc characteristics (v ss = 0v, v dd = 1 . 8 to 3.3 v, ta = - 40 to 85 c) item symbol condition min. typ. max. unit pin used operating volt age (1) v dd 1 . 8 - 3.3 v vdd ( *1 ) operating voltage (2) v0 4.0 - 1 5 .0 v v0 ( *2 ) high v ih 0. 8 v dd - v dd input voltage low v il v ss - 0. 2 v dd v ( *3 ) high v oh i oh = - 0.5ma 0. 8 v dd - v dd output voltage low v ol i ol = 0.5ma v ss - 0. 2 v dd v ( *4 ) input l eakage current i il v in = v dd or v ss - 1.0 - + 1.0 m a ( * 3) output leakage current i oz v in = v dd or v ss - 3.0 - + 3.0 m a ( * 5) lcd driver on resistance r on ta = 25 c, v0 = 8v - 2.0 3.0 k w segn comn ( * 6) operating frequency f fr ta = 25 c 1/128 duty, 9 pwm rext = 620k w ( * 11) 70 85 100 hz ( *7 ) (*11) 3 / x 4 2.4 - 3.3 v voltage converter input voltage v ci ?? 5 2.4 3.0 v v ci voltage converter output voltage v out x3 / 4 / 5 voltage conversion (no - load ) 95 99 - % vout voltage regulator operating vol tage v out 5.4 - 1 5 .0 v vout voltage follower operating voltage v0 4.0 - 1 1 .0 v v0 ( * 8) reference voltage v ref ta = 25 c 2.04 2.10 2.16 v ( * 9)
s6b 0729x 102 seg / 81 com driver & controller for stn lcd 61 dynamic current consumption when the internal power supply is on table 20 . dynamic current 2 (internal po wer) (v dd = 2.5 v, ta = 25 c) item symbol condition min. typ. max. unit pin used vci=2.5v, v0 - vss = 9.004 v, x 5 boosting, duty = 1/ 81 , normal mode (display off) - 60 - m a ( *10 ) vci=2.5v, v0 - vss = 9.004 v, x 5 boosting, duty = 1/ 81 , normal mode (display on , checker pattern) - 120 - m a ( * 10) dynamic current consumption i dd vci=2.5v, v0 - vss = 1 0 .0v, x 5 boosting, duty = 1/ 81 , on lcd module (display on , checker pattern) 400 m a current consumption during power save mode table 21. power save mode current (v dd = 2.5 v, ta = 25 c) item symbol condition min. typ. max. unit pin used sleep mode current i dds1 during sleep - - 2 m a (*10)
102 seg / 81 com driver & controller for stn lcd s6b 0729 x 62 table 22 . the relationship between oscillation frequency and frame frequency duty ratio item f cl f osc 1/n on - chip oscillator circuit is used f fr x n f fr x pwm x 2 x n (f osc : oscillation frequency, f cl : display clock frequency, f fr : frame frequency, n = 16 to 129 ) [* remark solves] *1 . though the wide range of operating voltages is guaranteed, a spike voltage c hange may affect the voltage assurance during access from the mpu. *2 . in case of external power supply is applied. *3 . csb, rs, db0 to db7, e_rd, rw_wr, resetb, ps1 , ps 0 , intrs and ref *4 . db0 to db7 *5 . applies when the db0 to db7 pins are in high i mpedance. *6 . resistance value when - 0.1[ma] is applied during the on status of the output pin segn or comn. ron [k w ] = d v[v] / 0.1[ma] ( d v : voltage change when - 0.1[ma] is applied in the on status.) *7 . see table 23 for the relationship between oscillation frequency and frame frequency. *8 . the voltage regulator circuit adjusts v0 within the voltage follower operating voltage range. *9 . on - chip reference voltage source of the voltage regulator circuit to adjust v0 . *10 . applies to the case where the on - chip oscillation circuit is used and no access is made from the mpu. the current consumption, when the built - in power supply circuit is on. the current flowing through voltage regulation resistors(rb and ra) is not included. it does not include the current of the lcd panel capacity, wiring capacity, etc. other conditions are 1/12 bias, 3 frc, 9 pwm, frame inversion, frame freq. = 85hz, bl=(9,9,9,0), dg=(6,6,6,0), lg=(3,3,3,0), wh= (0,0,0,0). *1 1. applies when pwm method is used. when both pwm and frc method are used, frame frequency should be increased up to more than 130hz. so, oscillator resistor value between osc1 and vdd pin should be reduced.
s6b 0729x 102 seg / 81 com driver & controller for stn lcd 63 ac characteri stics read / write characteristics (8080 - series mpu) t dh80 t od80 t ds80 t acc80 0.9v dd 0.1v dd t pwl t cy80 t ah80 t as80 db0 to db7 ( write ) db0 to db7 ( read ) /rd, /wr csb rs t pwh figure 38. read / write c haracteristics (8080 - series mpu) (v dd = 1 . 8 v, ta = - 40 ~ +85 c) item signal symbol condition min. max. unit address setup time address hold time rs t as80 t ah80 0 0 - - ns system cycle time for write system cycle time for read t cy80 t cy80 150 330 - ns pulse width low pulse width high / wr / rd t pwl t pwh 60 60 - - ns data setup time data hold time t ds80 t dh80 40 10 - - ns read access time output disable time db0 to db7 t acc80 t od80 cl = 100 pf 15 10 - 5 0 ns (v dd = 2.7 v, ta = - 40 ~ +85 c) item signal symbol condition min. max. unit address setup time address hold time rs t as80 t ah80 0 0 - - ns system cycle time for write system cycle time f or read t cy80 t cy80 100 166 - ns pulse width low pulse width high / wr / rd t pwl t pwh 40 40 - - ns data setup time data hold time t ds80 t dh80 30 5 - - ns read access time output disable time db0 to db7 t acc80 t od80 cl = 100 pf 15 10 - 5 0 ns note: *1. the input signal rise time and fall time (tr, tf) is specified at 15 ns or less. (tr + tf) < (t cy80 - t pwlw - t pwhw ) for write, (tr + tf) < (t cy80 - t pwlr - t pwhr ) for read
102 seg / 81 com driver & controller for stn lcd s6b 0729 x 64 read / write characteristics (6800 - series microprocessor) t dh68 t od68 t ds68 t acc68 0.1v dd 0.9v dd t ewh t ah68 db0 to db7 ( write ) db0 to db7 ( read ) e rs, r/w t ewl 0. 9 v dd 0. 1 v dd t ew l t cy68 t as68 csb t ew h figure 39. read / write characteristics (6800 - series microprocessor) (v dd = 1 . 8 v, ta = - 40 ~ +85 c) item signal symbol condition min. max. unit address setup time address hold time rs rw t as68 t ah68 0 0 - - ns system cycle time f or write system cycle time for read t cy68 t cy68 150 330 - ns enable width high enable width low e_rd (e) t ewh t ewl 60 60 - - ns data setup time data hold time t ds68 t dh68 40 10 - - ns read access time output disable time db0 to db7 t acc68 t od68 c l = 100 pf 15 10 - 5 0 ns (v dd = 2 . 7 v, ta = - 40 ~ +85 c) item signal symbol condition min. max. unit address setup time address hold time rs rw t as68 t ah68 0 0 - - ns system cycle time for write system cycle time for read t cy68 t cy68 100 166 - ns enab le width high enable width low e_rd (e) t ewh t ewl 40 40 - - ns data setup time data hold time t ds68 t dh68 30 5 - - ns read access time output disable time db0 to db7 t acc68 t od68 c l = 100 pf 15 10 - 5 0 ns note: *1. the input signal rise time and f all time (tr, tf) is specified at 15 ns or less. (tr + tf) < (t cy 68 - t ewhw - t ewlw ) for write, (tr + tf) < (t cy 68 - t ewhr - t ewlr ) for read
s6b 0729x 102 seg / 81 com driver & controller for stn lcd 65 serial interface characteristics db7 (sid) db6 (sclk) rs csb t dhs t dss t whs 0.9v dd 0.1v dd t wls t cys t ahs t ass t chs t css figure 40. serial interface charact eristics (v dd = 1 . 8 v, ta = - 40 ~ +85 c) item signal symbol condition min. max. unit serial clock cycle sclk high pulse width sclk low pulse width db6 (sclk) t cy s t w hs t w ls 111 60 60 - - - ns address setup time address hold time rs t ass t ahs 6 0 6 0 - - n s data setup time data hold time db7 (sid) t dss t dhs 6 0 6 0 - - ns csb setup time csb hold time csb t css t chs 6 0 1/2 * t cy s - - ns (v dd = 2 . 7 v, ta = - 40 ~ +85 c) item signal symbol condition min. max. unit serial clock cycle sclk high pulse width scl k low pulse width db6 (sclk) t cy s t w hs t w ls 58.8 30 30 - - - ns address setup time address hold time rs t ass t ahs 3 0 3 0 - - ns data setup time data hold time db7 (sid) t dss t dhs 3 0 3 0 - - ns csb setup time csb hold time csb t css t chs 3 0 1/2 * t cy s - - ns note: *1. the input signal rise time and fall time (tr, tf) is specified at 15 ns or less.
102 seg / 81 com driver & controller for stn lcd s6b 0729 x 66 reset input timing resetb internal status t rw t r reset complete during reset figure 41. reset input timing (v dd = 1 . 8 ~ 3 . 3 v, ta = - 40 ~ +85 c) item signal symbol condition min. max. uni t reset low pulse width resetb t rw 1 000 - ns reset time - t r - 1 000 ns
s6b 0729x 102 seg / 81 com driver & controller for stn lcd 67 reference applicatio ns microprocessor inter face in case of interfacing with 6800 - series (ps 0 = ?h?, ps1 = ?h?) db0 to db7 resetb v dd v dd rw e rs cs b 6800-series mpu cs b rs e_rd rw_wr db0 to db7 resetb ps0 ps 1 s6b0 7 29 figure 42. i nterfacing with 6800 - series (ps 0 = ?h?, c68 = ?h?) in case of interfacing with 8080 - series (ps 0 = ?h?, ps1 = ?l?) db0 to db7 resetb v ss v dd /wr /rd rs cs b 8080-series mpu cs b rs e_rd rw_wr db0 to db7 resetb ps0 ps 1 s6b 07 29 figure 43. i nterfacing with 8080 - series (ps 0 = ?h?, c68 = ?l?)
102 seg / 81 com driver & controller for stn lcd s6b 0729 x 68 in case of 4 - p in spi mode (ps0 = "l" , ps1 = " h " ) open resetb v ss sclk sid rs cs b mpu cs b rs db7(sid) db6(sclk) resetb db0 to db5 ps 0 ps 1 s6b 07 29 v dd figure 44. s erial interface (ps 0 = ?l?, ps 1 = ? h ?) in case of 3 - p in spi mode (ps0 = "l" , ps1 = "l" ) open resetb v ss sclk sid cs b mpu cs b db7(sid) db6(sclk) resetb db0 to db5 ps 0 ps 1 s6b0 7 29 v ss figure 45. s erial interface (ps 0 = ?l?, ps 1 = ?l?)
s6b 0729x 102 seg / 81 com driver & controller for stn lcd 69 connections between s6b0729 and lcd pane l single chip configuration (1/ 81 duty configurations) com 39 : com 0 coms0 coms1 com 79 : com 40 seg 101 ........... seg 0 s 6b 07 29 ( bottom view) com 39 : com 0 coms0 coms1 com 79 : com 40 seg 0 ............ seg 101 s 6b 07 29 ( top view) ? a x a ? a x a 80 1 02 pixels ? a x a ? a x a 80 1 02 pixels figure 46 . shl = 0, adc = 1 figure 47 . shl = 0, adc = 0 ? a x a ? a x a coms0 com 0 : co m39 co m79 : com 40 coms1 se g101 ........... se g0 s 6b 07 29 ( top view) ? a x a ? a x a 80 1 02 pixels com 40 : com 79 coms coms com 0 : com 39 seg 0 ........... seg 101 s 6b 07 29 ( bottom view) 80 1 02 pixels figure 48 . shl = 1, adc = 0 figu re 49 . shl = 1, adc = 1

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